1. Field of the Invention
The present invention relates to a semiconductor memory device including a boost circuit, more particularly to a semiconductor memory device which uses a voltage boosted for both of a memory cell array and an output circuit.
2. Description of the Related Art
In recent years, a voltage to be supplied to a semiconductor memory device from an external power source has been lowered. However, some circuits which are driven preferably by a higher voltage rather than such low voltage are included in internal circuits of the semiconductor memory device. As such circuit, there are, for example, an output circuit and a word line driving circuit.
Accordingly, as-outputted, voltage from the external power source is not supplied to the output circuit and the word line driving circuit, but a voltage obtained by boosting it by a boost circuit is supplied to them. This situation will be described using FIG. 7.
The semiconductor memory device shown in FIG. 7 comprises a memory cell array 26 and an output circuit 27. In the memory cell array 26, many memory cells are included and many word lines for accessing these memory cells are provided. As is well known, a voltage to be applied to the selected word line is higher than the power source voltage by more than a threshold voltage of a transistor. Furthermore, to increase an output speed of data, a voltage higher than the power source voltage is used also in the output circuit 27.
As described above, since the memory cell array 26 and the output circuit 27 need a voltage higher than the power source voltage, a voltage VBOOT which is obtained by boosting the external voltage by a boost voltage generating circuit 25 is supplied to the memory cell array 26 and the output circuit 27.
However, such a conventional semiconductor memory device involves the following problems. Specifically, the voltage VBOOT generated by the boost voltage generating circuit 25 is commonly used for the memory cell array 26 and the output circuit 27. Therefore, when the voltage VBOOT varies due to the operation of the output circuit 27, a driving voltage of the word line driven in the memory cell array varies. Particularly, when this semiconductor memory device is a synchronous DRAM, as its operation frequency becomes higher, the variation of the voltage VBOOT owing to the operation of the output circuit 27 becomes more significant. When the word line is driven in the memory cell array 26 in a situation where the voltage VBOOT is varying, a problem occurs in that poor reading-out/writing operation is brought about and the sensing speed is slowed.
On the contrary, the voltage VBOOT varies also due to the operation of the memory cell array 26. Accordingly, when the voltage VBOOT varies owing to the operation of the memory cell array 26, a performance of the output circuit 27 is degraded, so that a problem occurs that its output speed is lowered and an output timing becomes uneven among its output pins.
With reference to the synchronous DRAM, since data outputting and word line driving are simultaneously performed, the foregoing problem is serious.
On the other hand, when a high speed data outputting and an increase in an output current are desired, the voltage VBOOT for driving the output circuit 27 must be more elevated. However, since the voltage VBOOT is used also for the memory cell array 26, the voltage VBOOT can not be freely set. In other words, the voltage VBOOT must be set within a range which satisfies conditions demanded by the memory cell array 26 and the output circuit 27, so that the range is greatly restricted.
As described above, when the boost voltage VBOOT generated within the semiconductor memory device is shared by the memory cell array 26 and the output circuit 27, there has been a problem that noise interference between the output circuit 27 and the memory cell array 26 occurs and the range for setting the boost voltage VBOOT is greatly restricted so that it is difficult to allow the voltage VBOOT to have a degree of freedom.